Semiconductor wafer structure having si material and iii-n material on the (111) surface of the si material

ABSTRACT

A semiconductor wafer structure includes a substrate, Si material on the substrate, the Si material having a thickness of 100 μm or less and a (111) surface facing away from the substrate, and III-N material on the (111) surface of the Si material. The substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si material. A GaN wafer having GaN material and a method of manufacturing an III-N substrate are also provided.

TECHNICAL FIELD

The instant application relates to III-N wafer structures, and moreparticularly to forming thick III-N wafer structures.

BACKGROUND

GaN offers several superior characteristics over Si as a semiconductormaterial for fabricating devices, such as lower threshold voltage, loweron-state resistance (Rdson), lower parasitic capacitance, lower gateresistance, and better FOM (figure of merit), resulting in tremendousperformance and size advantages over Si. With such advantages asapparent motivating factors, ongoing extensive efforts have been made inthe semiconductor industry to improve the crystal quality of GaN. Forexample, GaN typically has a high defect density attributable to sliplines resulting from lattice mismatch between the growth substrate andthe GaN epitaxy e.g. −17% in the case of GaN on Si(111). Reducing defectdensity caused by slip lines yields an improvement of device performancein many cases, e.g. power devices such as GaN-based HEMTs (high electronmobility transistors). In addition to the GaN epitaxy itself, theunderlying buffer layer(s) should also have good crystal quality.Acceptable GaN crystal quality has been realized to date by using Sigrowth substrates which are relatively inexpensive. GaN crystal qualityimproves by increasing the thickness of the deposited GaN layer.

However, the maximum thickness of GaN grown on Si is limited by thedifference in coefficient of thermal expansion (CTE) between the twomaterials. The CTE of GaN ranges from 5.6*10̂−6/K to 6.2*10̂−6/K dependingon the source. Si has a CTE of 2.6*10̂−6/K. Deposition of GaN istypically done at temperatures around 1000° C. (e.g. 1000-1200° C. forMOCVD—metal organic chemical vapor deposition). The deposited GaN layercracks during subsequent cooling if made too thick due to the severetensile stress induced by the smaller CTE of Si. The maximum thicknessof GaN deposited on Si is therefore in the range of 6-8 μm. If thickerGaN layers are needed, more expensive substrates are conventionally usedsuch as SiC, sapphire or very rare (pure) GaN substrates.

SUMMARY

According to an embodiment of a method of manufacturing an III-Nsubstrate, the method comprises: bonding a Si substrate to a supportsubstrate, the Si substrate having a (111) growth surface facing awayfrom the support substrate; thinning the Si substrate at the (111)growth surface to a thickness of 100 μm or less; and forming III-Nmaterial on the (111) growth surface of the Si substrate after the Sisubstrate is thinned. The support substrate has a coefficient of thermalexpansion more closely matched to that of the III-N material than the Sisubstrate.

According to an embodiment of a semiconductor wafer structure, the waferstructure comprises a substrate, Si material on the substrate, the Simaterial having a thickness of 100 μm or less and a (111) Si surfacefacing away from the substrate, and III-N material on the (111) Sisurface of the Si material. The substrate has a coefficient of thermalexpansion more closely matched to that of the III-N material than the Simaterial.

According to another embodiment of a method of manufacturing an III-Nsubstrate, the method comprises: providing a first substrate having afirst surface and a second surface opposing the first surface; formingan III-N material of a first thickness on the first surface of the firstsubstrate; removing the first substrate after the III-N material isformed at the first thickness; bonding a second substrate to a side ofthe III-N material, the second substrate having a coefficient of thermalexpansion more closely matched to that of the III-N material than thefirst substrate; and increasing the thickness of the III-N material to asecond thickness greater than the first thickness after the firstsubstrate is removed and the second substrate is bonded to the III-Nmaterial. The first thickness of the III-N material is sufficient toensure that the second substrate has no influence on the crystalstructure of the III-N material when the thickness of the III-N materialis increased from the first thickness to the second thickness.

According to an embodiment of a GaN wafer, the GaN wafer comprises GaNmaterial. The GaN material has a diameter of at least 200 mm and athickness of at least 10 μm.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The components in the figures are not necessarily to scale, emphasisinstead being placed upon illustrating the principles of the invention.Moreover, in the figures, like reference numerals designatecorresponding parts. In the drawings:

FIGS. 1A through 1C illustrate sectional views of a semiconductor waferstructure during different stages of a method of manufacturing III-Nmaterial on a growth substrate according to an embodiment;

FIGS. 2A through 2E illustrate sectional views of a semiconductor waferstructure during different stages of a method of manufacturing III-Nmaterial on a structured growth substrate according to a firstembodiment;

FIGS. 3A through 3C illustrate sectional views of a semiconductor waferstructure during different stages of a method of manufacturing III-Nmaterial on a structured growth substrate according to a secondembodiment;

FIG. 4 illustrates a sectional view of a structured substrate forgrowing III-N material according to a third embodiment;

FIGS. 5A through 5C illustrate sectional views of a semiconductor waferstructure during different stages of a method of manufacturing III-Nmaterial on a structured growth substrate according to a fourthembodiment;

FIGS. 6A and 6B illustrate sectional views of a semiconductor waferstructure during different stages of a method of manufacturing III-Nmaterial on a structured growth substrate according to a fifthembodiment;

FIG. 7 illustrates a sectional view of a structured substrate forgrowing III-N material according to a sixth embodiment;

FIG. 8 illustrates a sectional view of a structured substrate forgrowing III-N material according to a seventh embodiment; and

FIGS. 9A through 9H illustrate sectional views of a semiconductor waferstructure during different stages of a method of manufacturing III-Nmaterial in different stages according to an embodiment.

DETAILED DESCRIPTION

Embodiments described herein provide for the deposition of relativelythick GaN layers e.g. 10 μm or more thick of good crystal quality. Thesame processes described herein can yield thinner GaN layers if desired.In each case, inexpensive substrates such as Si can be used to depositGaN layers of different thicknesses. Si substrates are of particularinterest due to wide availability in large diameters e.g. ranging from200 mm (so-called ‘8 inch’) to 300 mm (so-called ‘12 inch’) or evenlarger such as 450 mm (so-called ‘18 inch’). High crystal quality III-Nmaterial which yields better device characteristics can be realizedusing the embodiments described herein. Also the maximum voltage betweenthe device and substrate is no longer limited according to theembodiments described herein, which can be of particular interest sincethe superior characteristics of GaN are best suited for devices withhigh breakdown voltage.

Described next are embodiments which involve bonding a growth substratefor III-N material to a support substrate that is better CTE-matched tothe III-N material than the growth substrate, and thinning the growthsubstrate so that only a thin growth layer remains e.g. about 100 μm orless. The thin growth layer determines the lattice of the subsequentlydeposited III-N layer and the support substrate limits stress problemsduring cooling down after the III-N epitaxy. In some embodiments, thegrowth layer on the support substrate can be structured in a way whichis beneficial for the subsequent III-N epitaxy and/or reduces stress.

FIGS. 1A through 1C illustrate corresponding sectional views of asemiconductor wafer structure during different stages of a manufacturingprocess according to an embodiment. According to this embodiment, a Sisubstrate 100 is bonded to a support substrate 102 using any suitableknown bonding process as shown in FIG. 1A. The Si substrate 100 has a(111) growth surface 101 (or other orientation) facing away from thesupport substrate 102, and the substrates 100, 102 have different CTEs.The Si substrate 100 is thinned at the (111) growth surface 101 to athickness (Tthin) of 100 μm or less e.g. 10 μm or less using anysuitable known thinning process such as wet chemical etching, CMP(chemical mechanical polishing), etc. as shown in FIG. 1B. Thermalexpansion which occurs during subsequent formation of III-N material onthe thinned Si substrate 100 is dominated by the support substrate 102instead of by the Si substrate 100 because the Si substrate 100 issignificantly thinner (and therefore has much less bulk) than thesupport substrate 102. This in turn reduces the likelihood of crackingof the III-N material because the support substrate 102 is selected sothat the CTE of the support substrate 102 is relatively well matched tothat of the III-N material, or at least more closely matched to theIII-N material than the thinned Si substrate 100.

After the Si substrate 100 is thinned, the III-N material 104 such asGaN, AlN, InN, etc. is formed on the (111) growth surface 101 of thethinned Si substrate 100 using any suitable known process such as MOCVDas shown in FIG. 1C. The III-N material 104 is less prone to crackingduring subsequent cooling, because the support substrate 102 has a CTEmore closely matched to that of the III-N 104 material than the Sisubstrate 100 and the Si substrate 100 was thinned prior to formation ofthe III-N material 104. With such an III-N growth process, somestructural damage can still arise in the resulting III-N material 104(also cracks in the Si layer would be minimized). To prevent thepossible occurrence of such structural damage, the thinned Si substrate100 can be structured prior to formation of the III-N material 104 in away which is beneficial for the III-N epitaxy and/or reduces stress.

FIGS. 2A through 2E illustrate corresponding sectional views of asemiconductor wafer structure during different stages of a manufacturingprocess in which the Si substrate 100 is structured prior to formationof the III-N material 104, according to a first embodiment. FIG. 2Ashows the Si substrate 100 after trenches 106 are formed in the Sisubstrate 100 at a bonding surface 103 of the Si substrate 100 facingaway from the (111) growth surface 101. The trenches 106 can be formedin active regions and/or kerf regions (also commonly referred to asscribe lines) of the Si substrate 100. Any known suitable process suchas etching can be employed to form the trenches 106. The trenches 106are at least partly filled with a material 108 such as a dielectric(e.g. SiO₂) before the Si substrate 100 is bonded to the supportsubstrate 102 at the bonding surface 103. The material 108 fills thetrenches 160 and also covers the bonding surface 103 of the Si substrate100 according to this embodiment. Alternatively, the trenches 106 canremain open at the time of bonding to the support substrate 102 andlater filled before III-N deposition.

FIG. 2B shows the semiconductor wafer structure after the supportsubstrate 102 is bonded to the material 108 covering the bonding surface103 of the Si substrate 100. Any suitable support substrate 102 can beused so long as the support substrate 102 has a CTE more closely matchedto the CTE of the III-N material 104 to be formed on the Si substrate100 than to the CTE of the Si substrate 100.

FIG. 2C shows the semiconductor wafer structure after the Si substrate100 is thinned at the (111) growth surface 101 of the Si substrate 100.The Si substrate 100 is thinned to a thickness of 100 μm or less e.g. 10μm or less to limit stress on the III-N material 104 to be subsequentlyformed. According to this embodiment, thinning of the Si substrate 100results in the trenches 106 being exposed at both the (111) growthsurface 101 and the bonding surface 103 so that the thinned Si substrate100 is separated into islands of Si material 110. Alternatively, thetrenches 106 can be exposed only at the (111) growth surface 101 so thatthe thinned Si substrate 100 is not fully separated into islands i.e.the thinned Si substrate 100 remains continuous near the bonding surface103.

FIG. 2D shows the semiconductor wafer structure during deposition of theIII-N material 104 e.g. by an MOCVD-based epitaxial lateral overgrowth(ELOG) process. The III-N material 104 (e.g. GaN with one or more bufferlayers) deposits on the exposed (111) growth surface 101 of the thinnedSi substrate 100. Small voids may form on the dielectric material 108 inthe trenches 106. The III-N material 104 continues to grow bothvertically and horizontally (laterally) on the Si islands 110 asillustrated by the different sized rectangular boxes shown in FIG. 2D.The III-N material 104 of course grows in this way over all of the Siislands 110, even though FIG. 2D shows the growth over just one of theislands 110 for ease of illustration.

FIG. 2E shows the semiconductor wafer structure after the III-N material104 is deposited on the thinned Si substrate 100 to any desiredthickness e.g. 10 μm or thicker. Thermal expansion which occurs duringformation of the III-N material 104 is dominated by the thicker supportsubstrate 102 instead of the thinned Si substrate 100. Thinning the Sisubstrate 100 prior to deposition of the III-N material 104 togetherwith the trench structures 106 formed in the thinned Si substrate 100reduces the likelihood of cracking of the III-N material 104, becausethe CTE of the support substrate 102 is closer to that of the III-Nmaterial 104 than the thinned Si substrate 100. The majority ofslip-lines which result in the III-N material 104 tend to be disposedover the Si islands 110 and not the trenches 106. As such, first regions112 of the III-N material 104 over the Si islands 110 have a higherdensity of slip lines than second regions 114 of the III-N material 104over the trenches 106. Devices can be formed in the second regions 114of the III-N material 104 i.e. the regions with a lower density of sliplines to ensure better device performance. In this case, it would bebeneficial to form the trenches 106 wider than the Si islands 110.However for relatively thin layers as compared to the thickness of theIII-N layer 104, forming the Si islands 110 wider than the trenches 106yields better planarity.

FIGS. 3A through 3C illustrate corresponding sectional views of asemiconductor wafer structure during different stages of a manufacturingprocess in which the Si substrate 100 is structured prior to formationof the III-N material 104, according to a second embodiment. FIG. 3Ashows the Si substrate 100 after trenches 106 are formed in the Sisubstrate 100 at the bonding surface 103 of the substrate 100 facingaway from the (111) growth surface 101, the material 108 filling thetrenches 106 is removed from the bonding surface 103 of the Si substrate100, and additional (optional) Si 116 is formed at the bonding surface103 of the Si substrate 100 e.g. by epitaxy after the material 108 isremoved from the bonding surface 103. If the optional additional Silayer 116 is provided, the material 108 in the trenches 106 issurrounded on all sides by Si and the support substrate 102 bonded tothe Si substrate 100 is separated from the material 108 in the trenches106 by the additional Si layer 116 as shown in FIG. 3A.

FIG. 3B shows the semiconductor wafer structure after the Si substrate100 is thinned at the (111) growth surface 101 of the Si substrate 100.The Si substrate 100 is thinned at the (111) growth surface 101 to athickness of 100 μm or less e.g. 10 μm or less. According to thisembodiment, thinning of the Si substrate 100 results in the trenches 106being exposed only at the (111) growth surface 101 so that the Sisubstrate 100 is not separated into islands of Si material (if theoptional Si layer 116 is grown) after thinning. Such a structure isrealized by the growth of the additional Si layer 116 after trenchformation.

FIG. 3C shows the semiconductor wafer structure after the III-N material104 is formed e.g. by MOCVD on the thinned Si substrate 100 to anydesired thickness e.g. 10 μm or thicker. This embodiment is well-suitedfor quasi-vertical devices i.e. devices having a current path with alateral component and a vertical component as represented by the arrowin FIG. 3C. Such devices have a gate 118 which controls the underlyingchannel, and two terminals 120, 122 spaced apart by the channel. Eitherterminal 120, 122 (i.e. the source or drain) of the device extends tothe underlying thinned Si substrate 100 which can be doped so that thethinned Si substrate 100 is electrically conductive. Because theinsulating material 108 filling the trenches 106 was previously removedfrom the bonding surface 103 of the Si substrate 100, the current pathcontinues unobstructed to the doped Si substrate 100 according to thisembodiment.

FIG. 4 illustrates a third embodiment where the trenches 106 in thethinned Si substrate 100 are not filled with any material prior todeposition of the III-N material 104. As such, the trenches 106 remainopen at the (111) growth surface 101 of the Si substrate 100 when theIII-N material 104 begins forming on the (111) growth surface 101. Thetrenches 106 can be etched all the way to the underlying supportsubstrate 102 to form islands (dies) of Si completely separated from oneanother. During subsequent high-temperature MOCVD processing to form theIII-N material 104, only individual island (die) stresses are presentand not entire wafer stress. This in turn leads to less wafer bow andtherefore a thicker Si substrate 100 can be used to support the growthof the III-N material 104. Of course, smaller wafer bow has multiplebenefits: less risk of cracks; easier handling; etc.

FIGS. 5A through 5C illustrate corresponding sectional views of asemiconductor wafer structure during different stages of a manufacturingprocess in which the Si substrate 100 is structured prior to formationof the III-N material 104, according to a fourth embodiment. FIG. 5Ashows the Si substrate 100 after trenches 106 are formed in the Sisubstrate 100 at the bonding surface 103 and the trenches 106 are filledwith a material 108. According to this embodiment, the width (W_(T)) ofthe trenches 106 is greater than the width (W_(Si)) of the Si islands110 between the trenches 106 and the trenches 106 are filled with adielectric material 108 such as SiO₂. The dielectric-filled trenches 106are broader than the narrow Si islands 110 interposed between thetrenches 106. Such a structure is well suited for MOCVD-based ELOG.

FIG. 5B shows the semiconductor wafer structure during ELOG of the III-Nmaterial 104 on the (111) growth surface 101 of the Si islands 110. Thedifferent sized rectangular boxes in FIG. 5B represent the lateralgrowth of the III-N material 104 at different stages of the ELOGprocess. The III-N material 104 eventually grows over the widedielectric-filled trenches 106.

FIG. 5C shows the semiconductor wafer structure after the III-N material104 is completely formed. As explained previously herein, the majorityof slip-lines in the III-N material 104 resulting from the epitaxiallateral overgrowth process are disposed over the Si islands 110 insteadof the dielectric-filled trenches 106. Accordingly, active deviceregions represented by the dashed box in FIG. 5C can be formed in theregions 114 of the III-N material 104 disposed over thedielectric-filled trenches 106 where the slip-line density is lower. Theregions 112 of the III-N material 104 over the Si islands 110 can beused e.g. as device isolation regions or as inactive regions later usedto separate the dies.

FIGS. 6A and 6B illustrate corresponding sectional views of asemiconductor wafer structure during different stages of a manufacturingprocess in which the Si substrate 100 is structured prior to formationof the III-N material 104, according to a fifth embodiment. FIG. 6 Ashows the wafer structure after the trenches 106 in the Si substrate 100are filled with at least two different materials 124, 126. For example,the trenches 106 can be partly filled with a first dielectric 124 suchas SiO₂ and then completely filled with a different material 126 e.g.which provides additional stress reduction/accommodation or iselectrically conductive and provides a point of contact between opposingsides of the structure. In the embodiment shown in FIG. 6A, an innerpart of the trenches 106 is filled with an electrically conductivematerial 126 such as doped Si or a metal such as W, T, TiN, metal alloy,etc. to form low-ohmic contacts. An outer part of the trenches 106surrounding the inner part is filled with an electrically insulatingmaterial 124.

FIG. 6B shows the structure after the III-N material 104 is formed onthe (111) growth surface 101 of the Si substrate 100. Quasi-verticaldevices can be formed in the III-N material 104 as represented by thegate, drain and source terminals 118, 120, 122 shown in FIG. 6B. In thiscase, the source 122 terminal extends through the III-N material 104 tothe electrically conductive inner part 126 of the trenches 106. Theconductive inner part 126 of the trenches 106 provide a current pathbetween the source terminal 122 and the underlying substrate 100 whichcan be heavily doped to ensure a good electrical connection. The drainterminal 120 instead can be electrically connected to the doped Sisubstrate 100 via the conductive inner part 126 of the trenches 106instead of the source terminal 122.

FIG. 7 illustrates a sectional view of a structured Si substrate 100prior to formation of III-N material 104 on the Si substrate 100,according to a sixth embodiment. The material 108 partly fills thetrenches 106 in the Si substrate 100 by lining the sidewalls and top ofeach trench 106 so that the trenches 106 are enclosed. The enclosedinner part 107 of the trenches 106 is filled with a gas. The III-Nmaterial 104 grows on the exposed parts of the Si substrate 100 alongthe (111) growth surface 101, eventually growing over the enclosedtrenches 106.

FIG. 8 illustrates a sectional view of a structured Si substrate 100prior to formation of III-N material 104 on the Si substrate 100,according to a seventh embodiment. The embodiment shown in FIG. 8 issimilar to the one shown in FIG. 7, however, the material 108 lining thesidewalls of the trenches 106 does not enclose the trenches 106.Instead, the trenches 106 remain open at the (111) growth surface 101 ofthe Si substrate 100 during the III-N formation process.

According to each of the previously described embodiments, asemiconductor wafer structure is provided which comprises a substrate,Si material on the substrate, the Si material having a thickness of 100μm or less and a (111) Si surface facing away from the substrate, andIII-N material on the (111) Si surface of the Si material. The Simaterial can be structured or not structured. The substrate has a CTEmore closely matched to that of the III-N material than the Si material.The substrate can be removed or remain in place during subsequent use infabricating devices in the III-N material. The III-N material can begrown to any desired thickness according to the embodiments describedabove. In one embodiment, the III-N material is GaN and the GaN materialhas a diameter of at least 200 mm and a thickness of at least 10 μm.Such a wafer structure can be used e.g. for GaN-on-GaN epitaxy. Inaddition, several of the embodiments previously described show anovergrown dielectric. Alternatively, a larger area can be provided withthe dielectric exposed so that even after overgrowth there is asignificant topology that can be used as an alignment mark.

Described next are embodiments which involve using two separatedeposition stages to form an III-N layer of a desired final thickness.In the first deposition stage, a growth wafer is used which is suitedfor growing a thin layer of III-N material such as GaN (e.g. a Si wafercan be used). The growth wafer is removed after the first depositionstage and replaced by a new substrate. The new substrate has a CTE moreclosely matched to the III-N material than the original growth wafer(e.g. a SiGe wafer with high Ge content or BeO can be used as the secondsubstrate). In this way, cracking of the III-N material is avoided whilethe structure cools down after the multi-stage deposition process iscompleted. The III-N material is grown thick enough in the firstdeposition stage so that the second substrate has no effect on thecrystal quality of the GaN during the second deposition stage.

FIGS. 9A through 9H illustrate corresponding sectional views of asemiconductor wafer structure during different stages of a two-stageIII-N deposition manufacturing process according to an embodiment. FIG.9A shows a first (growth) substrate 200 with first and second opposingsurfaces 201, 203 after III-N material 202 of a first thickness (T1) isformed on the first surface 201 of the growth substrate 200 e.g. byMOCVD. Any suitable III-N material 202 can be formed such as GaN, AlN,InN, etc. and/or combinations thereof. The III-N material 202 need onlybe thick enough to be mechanically stable during the subsequent bondingprocess. Steps to gradually improve crystal quality are not necessary inthe first deposition stage. For example, deposition of a buffer or seedlayer can be enough as the initial III-N material 202. Crystal qualityoptimization steps can be taken in the second deposition stage.

In one embodiment, the III-N material 202 is GaN, the growth substrate200 is a Si wafer, and the GaN 202 (including and buffer layers such asAlN) is deposited on the (111) surface 201 (or other orientation) of theSi wafer 200. FIG. 9A includes an exploded view which shows GaN material202 (with one or more buffer layers) deposited on the Si wafer 200. Thegrowth direction of the GaN material 202 is represented by an upwardfacing arrow in FIG. 9A. Each layer of GaN 202 includes a lower layer ofnitrogen (N) atoms and an upper layer of gallium (Ga) atoms as depictedin the exploded view of FIG. 9A. The common orientation for MOCVD isshown in FIG. 9A. However, the orientation can be flipped e.g. by usingMBE (molecular beam epitaxy). In each case, the maximum thickness of theinitial III-N material 202 is limited by the different CTEs of the III-Nmaterial 202 and the growth substrate 200. The crystal quality of theIII-N material 202 improves with increased thickness, however, crackingcan occur in the III-N material 202 during post-deposition cooling ifthe III-N material 202 is grown too thick in the first deposition stage.

FIG. 9B shows the semiconductor wafer structure after a second(temporary) substrate 204 is bonded to the growth side 205 of the III-Nmaterial 202. The temporary substrate 204 is provided for flipping theIII-N material 202 so that the original growth side 205 (i.e. the layerwith Ga atoms in the case of GaN) is eventually exposed during thesecond deposition stage. As such, any substrate can be used since thetemporary substrate 204 merely provides a mechanical flipping function.For example, a glass wafer or even a Si wafer can be used since thetemporary substrate 204 can be reused. The temporary substrate 204 canbe something other than a wafer, such as a thick deposition of astabilization layer on the III-N material 202. If the other (non-growth)side 207 of the III-N material 202 is sufficient for epitaxialdeposition (e.g. the layer with N atoms in the case of GaN), then thetemporary substrate 204 can be excluded. The temporary substrate 204 canbe bonded or deposited on the growth side 205 of the III-N material 202.

FIG. 9C shows the semiconductor wafer structure after the growthsubstrate 200 is removed e.g. by wet chemical etching in the case of aSi growth wafer. Other removal processes can be used instead or inaddition e.g. such as CMP (chemical mechanical polishing).

FIG. 9D shows the semiconductor wafer structure after the structure isflipped so that the temporary substrate 204 is below the III-N material202. The non-growth side 207 of the III-N material 202 (e.g. the layerwith N atoms again in the case of GaN) is exposed at the top side of thestructure after flipping.

FIG. 9E shows the semiconductor wafer structure after a third (support)substrate 206 is bonded to the III-N material 202 at the non-growth side207 of the III-N material 202. The support substrate 206 has a CTE moreclosely matched to that of the III-N material 202 than the originalgrowth substrate 200. The support substrate 206 can be bonded ordeposited on the III-N material 202. The support substrate 206 will beunder the III-N material 202 during the second deposition stage, isstable enough to withstand the epitaxy process, and has a similar CTE asthe III-N material 202. In one embodiment, the support substrate 206 isa germanium (Ge) wafer. Germanium has a CTE of 6.0E−6/K (GaN has a CTEof 5.6E−6/K), and allows much thicker layers than Si substrates (whichhave a CTE of 2.6E−6/K). A GaAs wafer (GaAs has a CTE of 6.2*10̂−6/K) canalso be used. Depending on the epitaxy temperature, a Ge or GaAs supportwafer 206 can be alloyed with Si to make the wafer 206 more thermallystable even though doing so reduces the overall CTE of the supportsubstrate 206.

For deposition at lower temperatures, pure Ge can be used. The CTE canbe even better matched to the III-N material 202 by choosing appropriatealloys. The support substrate 206 can be manipulated e.g. by sealing thesupport substrate 206 against out-diffusion or doping the supportsubstrate 206 for decreased electrical resistance. Such manipulationscan be employed so long as bonding to the III-N material 202 is goodenough to withstand the following epitaxy during the second depositionstage. A single crystal wafer need not necessarily be used as thesupport substrate 206. Still other types of support substrates 206 canbe used such as SiGe or BeO, and depends on the type of III-N material202 being formed. In each case, the lattice structure of the supportsubstrate 206 is not important because the III-N material 202 was madethick enough in the first deposition stage so that the crystal structureof the support substrate 206 does not influence the III-N material 202during the second deposition stage.

FIG. 9F shows the semiconductor wafer structure after the temporarysubstrate 204 is removed and the semiconductor wafer structure isflipped so that the support substrate 206 is below the III-N material202. The original growth side 205 of the III-N material 202 (e.g. thelayer with Ga atoms in the case of GaN) is exposed at the top side ofthe structure after flipping.

FIG. 9G shows the semiconductor wafer structure after the thickness ofthe III-N material 202 is increased to a second thickness (T2) greaterthan the first (initial) thickness (T1) e.g. by MOCVD during the seconddeposition stage. The first thickness T1 of the III-N material 202realized during the first deposition step is sufficient to ensure thatthe support substrate 206 has no influence on the crystal structure ofthe III-N material 202 as the thickness of the III-N material 202increases during the second deposition stage. As such, the III-Nmaterial 202 can be grown as thick as desired. The III-N material 202can be made thick enough to have the desired crystal quality, breakdownvoltage to the substrate 206 or even to be mechanically stable withoutthe support substrate 206. Further bonding(s) can be used to combine theIII-N material 202 with another substrate if needed for the final devicee.g. for electrical reasons.

The second deposition can be directly on the III-N material 202,resulting in very good crystal quality. A cleaning/surface preparationstep can be performed because of all the bonding. The new layer 208grows in the same direction as the initial layer 210 formed during thefirst deposition stage according to this embodiment. This isparticularly advantageous for III-N semiconductors.

However, the new layer 208 of the III-N material 202 can grow in theopposite direction by omitting the temporary substrate 204 andeliminating the flipping steps shown in FIGS. 9B through 9D. It may benecessary to still use the original growth side 205 of the III-Nmaterial 202 for electrical devices e.g. if a breakdown to the substrateneeds to be avoided in a horizontal device. In this case, the secondepitaxy begins to grow in a region of worse crystal quality. So roughlythe same thickness needs to be grown as during the first epitaxy toreach the same defect density on the surface. Since the second epitaxydoes not benefit from the first epitaxy, the first epitaxy can be veryshort. In each case, the CTE of the support substrate 206 is closeenough to that of the III-N material 202 so that little or no crackingoccurs in the III-N material 202 during post-deposition cooling. If thedeposition of the second layer 210 of the III-N material 202 is thickenough to be mechanically stable, the support substrate 206 can becompletely removed by any suitable means such as wet chemical etching,CMP, etc.

FIG. 9H shows the semiconductor wafer structure after the supportsubstrate 206 is removed from the III-N material 202 and after thethickness of the III-N material 202 is increased to the second thicknessT2. The III-N material 202 can be grown to any desired thicknessaccording to the embodiments described herein. In one embodiment, theIII-N material 202 is GaN and the GaN material 202 has a diameter (D) ofat least 200 mm and a thickness (T2) of at least 10 μm. Such a waferstructure can be used e.g. for GaN-on-GaN epitaxy.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the device in additionto different orientations than those depicted in the figures. Further,terms such as “first”, “second”, and the like, are also used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having”, “containing”, “including”,“comprising” and the like are open-ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a”, “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

With the above range of variations and applications in mind, it shouldbe understood that the present invention is not limited by the foregoingdescription, nor is it limited by the accompanying drawings. Instead,the present invention is limited only by the following claims and theirlegal equivalents.

What is claimed is:
 1. A semiconductor wafer structure, comprising: asubstrate; Si material on the substrate, the Si material having athickness of 100 μm or less and a (111) surface facing away from thesubstrate; and III-N material on the (111) surface of the Si material,wherein the substrate has a coefficient of thermal expansion moreclosely matched to that of the III-N material than the Si material. 2.The semiconductor wafer structure of claim 1, wherein the Si materialhas a thickness of 10 μm or less.
 3. The semiconductor wafer structureof claim 1, wherein the III-N material comprises GaN and has a thicknessof at least 10 μm.
 4. The semiconductor wafer structure of claim 1,further comprising a plurality of trenches extending from the (111)surface into the Si material.
 5. The semiconductor wafer structure ofclaim 4, wherein the trenches are filled with a material.
 6. Thesemiconductor wafer structure of claim 5, wherein the material is adielectric.
 7. The semiconductor wafer structure of claim 4, wherein thetrenches segment the Si material into islands of Si material separatedfrom each other by the trenches.
 8. The semiconductor wafer structure ofclaim 4, wherein the substrate is separated from a bottom of thetrenches by an additional layer of Si.
 9. The semiconductor waferstructure of claim 4, wherein the trenches are wider than the Simaterial between the trenches.
 10. The semiconductor wafer structure ofclaim 4, wherein the trenches are filled with at least two differentmaterials.
 11. The semiconductor wafer structure of claim 10, wherein aninner part of the trenches is filled with an electrically conductivematerial and an outer part of the trenches surrounding the inner part isfilled with an electrically insulating material.
 12. A method ofmanufacturing an III-N substrate, the method comprising: providing afirst substrate having a first surface and a second surface opposing thefirst surface; forming an III-N material of a first thickness on thefirst surface of the first substrate; removing the first substrate afterthe III-N material is formed at the first thickness; bonding a secondsubstrate to a side of the III-N material, the second substrate having acoefficient of thermal expansion more closely matched to that of theIII-N material than the first substrate; and increasing the thickness ofthe III-N material to a second thickness greater than the firstthickness after the first substrate is removed and the second substrateis bonded to the III-N material, the first thickness being sufficient toensure that the second substrate has no influence on the crystalstructure of the III-N material when the thickness of the III-N materialis increased from the first thickness to the second thickness.
 13. Themethod of claim 12, wherein the first substrate comprises Si, the firstsurface of the first substrate is a (111) Si surface, and the III-Nmaterial comprises GaN and one or more buffer layers formed on the (111)Si surface.
 14. The method of claim 12, wherein bonding the secondsubstrate to an exposed side of the III-N material comprises: bonding athird substrate to a side of the III-N material facing away from thefirst substrate; removing the first substrate after the third substrateis bonded to the III-N material to expose a side of the III-N materialpreviously covered by the first substrate; and bonding the secondsubstrate to the exposed side of the III-N material.
 15. The method ofclaim 12, further comprising removing the second substrate from theIII-N material after the thickness of the III-N material is increased tothe second thickness.
 16. A GaN wafer comprising GaN material, the GaNmaterial having a diameter of at least 200 mm and a thickness of atleast 10 μm.